Short answer: ECC memory (error-correcting code memory) is RAM that stores a few extra check bits with every word of data. The memory controller uses them to correct any single flipped bit on the fly and to detect two flipped bits, instead of passing corrupted data to the CPU without anyone noticing. It is standard in servers and workstations because memory errors are far more common than most people assume — and because a server holds other people’s data for months without a reboot.
Why does memory need error correction?
A DRAM cell is a tiny capacitor holding a charge, and that charge can be disturbed. Particle strikes from cosmic radiation, electrical noise and heat cause random soft errors; ageing or faulty cells cause hard errors that recur at the same address. Without ECC, a flipped bit is simply wrong data: a changed number in a database row, a corrupted byte in a file being written, or an invalid pointer that crashes a process or the kernel.
The best-known field data comes from Google’s server fleet. A 2009 study by Schroeder, Pinheiro and Weber, “DRAM Errors in the Wild”, found that about a third of machines and over 8% of memory modules saw at least one correctable error per year — rates far higher than lab estimates — and that errors tended to repeat on the same modules, which points at failing hardware more than at random strikes. Correctable errors on a module were also a strong warning of uncorrectable ones later.
How does ECC memory work?
A normal DDR4 module delivers 64 bits per transfer. An ECC module is 72 bits wide: 64 data bits plus 8 check bits, held on extra memory chips. When data is written, the memory controller computes the check bits from the data; when it is read back, it computes them again and compares.
- Single-bit error: the mismatch pattern says exactly which bit flipped, and the controller corrects it before the CPU sees the data. The program never knows.
- Two-bit error: detected but not correctable. The system raises a machine-check error instead of using bad data.
- Every event is logged. The controller counts corrected and uncorrected errors per module, which is how failing RAM is found before it does damage.
This scheme is called SECDED — single error correction, double error detection — and is built on Hamming codes. Servers often go further: Chipkill and similar “advanced ECC” modes spread each word across chips so that the failure of a whole memory chip is still correctable, and patrol scrubbing reads through all memory in the background so single-bit errors are fixed before a second one lands in the same word.
What happens when ECC cannot correct an error?
The CPU raises a machine-check exception. On Linux, an uncorrected error in memory the kernel can give up — a page of a user process, a clean page cache page — is handled by removing that page and killing the process that used it; an error in kernel memory usually means a panic. Either way the result is a crash you can see and investigate, not silent corruption that is written to disk and copied into your backups.
Does ECC protect against Rowhammer?
Partly. Rowhammer attacks flip bits in a DRAM row by rapidly accessing the rows next to it, and they were shown to work from ordinary programs and even JavaScript. ECC turns most single flips into corrected errors and logs them, which makes attacks far harder and much noisier — but researchers have demonstrated patterns that flip several bits in one word, beyond what SECDED can correct. ECC is one layer of defence against Rowhammer, alongside the refresh-rate and target-row-refresh mitigations in memory controllers and modules, not a complete fix.
ECC vs non-ECC memory
| Non-ECC | ECC | |
|---|---|---|
| Single-bit errors | Passed on as wrong data | Corrected transparently |
| Double-bit errors | Passed on | Detected, machine check raised |
| Error logging | None | Per-module counters, readable from the OS |
| Module width (DDR4) | 64 bits | 72 bits |
| Platform | Any desktop | CPU and motherboard must support it |
| Cost | Lower | Somewhat higher; extra chips |
| Performance | Baseline | Slightly lower; rarely measurable in server workloads |
ECC modules come unbuffered (ECC UDIMM, for workstations and small servers) or registered (RDIMM, with a register chip that lets a server carry many more modules). Registered DIMMs are always ECC. The two types do not mix, and a board must support the type you install.
Is DDR5 memory ECC memory?
No, although every DDR5 chip contains “on-die ECC”. JEDEC added it because DDR5 cells are so dense that the chips need internal correction to reach acceptable error rates at all. It corrects errors inside each chip, but it does not protect data on its way between the module and the memory controller, and it does not report what it corrected to the operating system. A server still needs side-band ECC — ECC DIMMs and a controller that checks them — to get correction across the whole path and the error counters. A consumer DDR5 module is non-ECC memory, whatever the box says about on-die ECC.
Who needs ECC memory?
- Databases and file servers — a flipped bit in a page that is then written back becomes permanent, and replicas faithfully copy it.
- ZFS and other checksumming file systems — they detect corruption on disk, but data that was corrupted in RAM before its checksum was computed is stored with a valid checksum. ECC closes that gap.
- Virtualisation hosts — one bad module can take down every VM on the machine.
- Long-running computation — scientific jobs, rendering, blockchain nodes, anything where a wrong result costs more than a crash.
- Servers with uptime measured in months — the longer data stays in RAM, the more chances it has to change.
A desktop for browsing and games gets by without it. For anything that stores data other people rely on, ECC is the baseline, not an upgrade.
How do you check whether a server has ECC?
On bare metal Linux, the firmware tables say what the board is configured for, and the kernel’s EDAC subsystem shows whether ECC is actually working:
# configured error correction, and module width: 72 total / 64 data = ECC
dmidecode -t memory | grep -E 'Error Correction Type|Total Width|Data Width'
# EDAC: corrected (ce) and uncorrected (ue) error counters per memory controller
grep . /sys/devices/system/edac/mc/mc*/ce_count /sys/devices/system/edac/mc/mc*/ue_count
# rasdaemon keeps a history of the events
apt install -y rasdaemon && systemctl enable --now rasdaemon
ras-mc-ctl --status
ras-mc-ctl --error-countNo /sys/devices/system/edac/mc directory usually means no EDAC driver for the platform or ECC disabled in the firmware. A ce_count that keeps climbing on one module means that module should be replaced soon, even though nothing has failed yet.
Get-CimInstance Win32_PhysicalMemoryArray | Select-Object MemoryErrorCorrection
# 6 = multi-bit ECC, 5 = single-bit ECC, 3 = noneECC memory at VMHeaven
Hi-CPU KVM and Pentesting KVM run on AMD EPYC servers with ECC memory. Standard KVM and DMCA Ignored KVM run on Intel servers with DDR4 ECC. On a dedicated server the hardware is yours to inspect: the dmidecode and EDAC commands above show exactly what is installed and whether it has logged errors.
Frequently asked
Does ECC memory slow a server down?
Slightly. Computing and checking the extra bits adds a little latency, and registered modules add a clock cycle, but the difference is rarely measurable in server workloads and far smaller than the cost of corrupted data.
Can I put ECC RAM in any computer?
Only if the processor and motherboard support it. Unbuffered ECC modules often run in a board without ECC support, but then without error correction; registered modules do not work in boards made for unbuffered memory.
How do I know whether my VPS uses ECC memory?
You cannot see it from inside the virtual machine: its dmidecode output describes virtual firmware, and corrected errors are handled on the host. Only the provider can state what the host hardware uses.